Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Heretofore, prescaling of dividend and divisor operands for division, particularly “high” fixed-radix division, was done by having one multiplier for prescaling the dividend and another multiplier for prescaling the divisor. By “high” fixed-radix division, it is generally meant radix integer values above radix 4. Radix-based division is linear in that each iteration improves the quotient estimate by a fixed proportion, i.e. a constant number of bits, and hence is referred to herein as fixed-radix division. The phrase “high fixed-radix” is used herein to describe the number of bits resolved in each iteration as being for radices greater than 4. Both of such multipliers received an estimate, which was over the reciprocal of the divisor, for such respective prescalings. The output of each of such dividend and divisor prescalings generally was in a non-redundant format, such as a two's complement format.
Multiplication of larger operands involves a larger multiplier circuit, hence greater delays. For dividend prescaling, the entire dividend was multiplied by the estimate using such multiplier, and as the dividend may be a significantly large number, meaning a significant delay. If a carry chain was used for such multiplication, such carry chain may be relatively long. This meant that the delay due to carry chain propagation was relatively long. While carry chains are typically used, carry chains are not necessarily used.